Modern computer architecture often employs a peripheral component interconnect (PCI) bus to connect peripheral components to a central or host system. As PCI technology evolved, various standards were developed in order to provide compatibility and continuity of PCI devices and architecture across a broad range of manufacturers and innovative devices. One recently developed standard is PCI-X 2.0.
One aspect of PCI-X 2.0 is that it is backwards compatible, that is, PCI-X 1.0 compliant systems can operate or be configured to operate on a PCI-X 2.0 compliant system. Another aspect of the PCI-X 2.0 standard is support for both 1.5 V and 3.3 V category-1 signaling. Generally, category-1 signals are a subset of PCI-X bus signals, as defined by the standard. Thus, a PCI-X 2.0 compliant host system detects the capabilities of all the plugged add-in cards in the system. In typical systems, this is achieved by sampling the PCIXCAP pin, a dedicated pin configured to identify the PCI-X mode of operation for a particular plugged add-in card. In particular, a PCI-X 2.0 compliant host system samples the PCIXCAP pin, determines the mode of operation, and provides the appropriate voltage level for the category-1 signals and other signals, according to the mode of operation.
In typical PCI systems, the mode of operation is often determined at a system reset or power-on reset (POR) time. That is, the PCI-X mode of operation is determined when the system is reset or first powered up. Typical system reset or POR operations often involve additional steps or operations beyond detecting the PCI-X mode of operation. For example, in response to a system reset or POR operation, a PCI-X system will typically initiate a PCI reset sequence that includes determining the PCI clock frequency, locking the phase locked loops (PLLs) to the PCI clock frequency, and generating an initialization pattern for the plugged add-in cards.
In many designs, the PCI initialization sequence begins after the POR signal is de-asserted. However, this requires the PCI reset to extend beyond the system POR, based on a variety of stabilization lag times and other delays. Moreover, some PCI-X compliant systems employ an external voltage regulator to modulate or otherwise maintain a consistent mode signal voltage, within a variation range as defined in the standard. Thus, the amount of time the PCI reset is extended can depend, in part, on the amount of time it takes for the external voltage regulator outputs to stabilize. As external voltage regulator output stabilization times can vary between differing types of voltage regulators, estimating a consistent stabilization time can be difficult and complex. Moreover, employing an estimated stabilization time based on the slowest voltage regulators can result in an extended PCI reset that is problematically long for some applications.
Therefore, there is a need for a system and/or method for voltage indicator signal generation that addresses at least some of the problems and disadvantages associated with conventional systems and methods.